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About Aldec Established in 1984, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. Active-HDL 10.1 supports design creation and simulation of the newest industry-leading FPGA devices from Altera, Lattice, Microsemi (Actel), Quicklogic and Xilinx. X-HDL translates structural, RTL and behavioral code and supports component libraries.
X-HDL performs translation of even the most complex RTL/gate-level code efficiently and requiring few, if any, 'hand tweaks' of the translated code. The high-performance, mixed-language solution interfaces with nearly one hundred twenty (120) third party vendor tools and provides FPGA designers a single platform that can be used independently of the targeted FPGA design flow. X-HDL 4 is a Verilog VHDL bi-directional translator. Active-HDL is an HDL-based FPGA Design and Simulation solution that supports the newest FPGA devices available from all leading FPGA vendors. Popular with designers for more than 15 years for FPGA design entry and simulation due to its award-winning and intuitive GUI and high performance simulator, Active-HDL now offers support for 64-bit simulation to meet the growing demand of simulation of larger designs.
1 (64bit) 478.7 mb Aldec, Inc., announces the latest release of its mixed-language FPGA design platform, Active-HDL 10.1.
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